Computers and other electronic equipment are useful for communicating, transmitting and storing information for retrieval at another location or later time. Unfortunately, extrinsic noise introduced by the electronic system or external system can cause error to occur in the transmitted or stored information.
Reed-Solomon (RS) codes are known and used for encoding and decoding information in such a way that induced errors are correctable. Such coding schemes are discussed in Error-Correction Coding for Digital Communications by George C. Clark, Jr. and J. Bibb Cain, published by the Plenum Press the contents of which are hereby incorporated by reference. The reader is directed to this book for additional information.
VLSI implementations of the decoder have been presented in the literature. K. Y. Liu in an article entitled "Architecture for VLSI Design of Reed-Solomon Decoders" IEEETC, Volume C-33, pages 178-179 (February 1984) discloses a system requiring 40 VLSI chips for the 100 support chips operated at 2.5 Mbits/second rate. A. M. Shao et al. in the article "A VLSI Design of a Pipeline Reed-Solomon Decoder" IEEETC, Volume C-34, pages 394-403 (May 1985) disclose an alternate implementation with no performance data given. Each of these designs utilize systolic arrays. The number of clock cycles required for error correction is dependent upon the number of errors. These implementations are thus not real-time decoders. A high-speed real-time Reed- Solomon decoder is needed for improved performance of error correction applications. The use of custom integrated circuits for such a Reed-Solomon decoder is desirable to reduce the number of integrated circuits necessary for the implementation.